Behavior of Faulty Double BJT BiCMOS Logic Gates'
نویسندگان
چکیده
Logic Behavior of Double BJT BiCMOS device under transistor level shorts and opens is examined. In addition to delay faults, faults that cause the gate to exhibit sequential behavior were observed. Several faults can be detected only by monitoring the current. The faulty behavior of Bipolar (TTL) and CMOS logic families is compared with BiCMOS, to bring out the testability differences.
منابع مشابه
A Clock Generator Driven by a Unified-CBiCMOS Buffer Driver for High Speed and Low Energy Operation
A new operation mode for a lateral unified-complementary BiCMOS (hereafter abbreviated as U-CBiCMOS) buffer driver based on a partially depleted CMOS/SOI process is proposed. The scheme utilizes a gated npn or pnp BJT inherent to a nor p-channel MOSFET. Forward current is applied to the base terminal of the channel MOSFET, with a normal pull-up or pull-down MOSFET as a current source, where eac...
متن کاملRF Characteristics of BJT Dev or Fully Ion-Implant
A selectively ion-implanted collector (SIC) is implemented in a 0.8 um BiCMOS process to improve the RF characteristics of the BJT devices. The SIC BJT device has better ft and fmax than the FIC (fully ion-implanted collector) BJT device because the extrinsic base-collector capacitance is reduced by the SIC process. The fmax is 9.5GHz and ft is 7.8 GHz for the SIC BJT device while the fmax is 7...
متن کاملA joint gate sizing and buffer insertion method for optimizing delay and power in CMOS and BiCMOS combinational logic
This paper presents the first reported joint gate sizing and buffer insertion method for minimizing the delay of power constrained combinational logic networks that can incorporate a mixture of unbuffered and buffered gates (or mixture of CMOS and BiCMOS gates). In the method, buffered gates in a network are decided on by an iterative process that uses a sequence of sizing optimizations where a...
متن کاملFault Characterization and Testability Analysis of Emitter Coupled Logic and Comparison with CMOS & BiCMOS Circuits
The logic behavior and performance of ECL gates under a set of defect models are examined. These are compared with equivalent set of BiCMOS and CMOS gates. It is found that logical fault testing is inadequate for obtaining a sufficiently high fault coverage, e.g., 79% for ECL versus 54% for BiCMOS and 69% for CMOS equivalent gates. Performance degradation faults such as delay, current and Volta...
متن کاملTestable Design of BiCMOS Circuits for Stuck-Open Fault Detection Using Single Patterns
Single BJT BiCMOS devices exhibit sequential behavior under transistor stuck-OPEN (+OPEN) faults. In addition to the sequential behavior, delay faults are also present. Detection of s-OPEN faults exhibiting sequential behavior needs two-pattern or multipattern sequences, and delay faults are all the more difficult to detect. A new design for testability scheme is presented that uses only two ex...
متن کامل